1. Field of the Invention
This invention relates generally to the electronic package. More particularly, this invention relates to a novel packaging configuration by directly attaching chips on to a printed circuit board (PCB) as multiple chip module (MCM) to simplify assembling and testing processes. A new repair-chip ready site to repair a failed DCA chip of the MCM module is provided such that a simplified "package-less" packaging technology is provided where the conventional procedure of single-chip packaging and testing processes are now eliminated.
2. Description of the Prior Art
There is a challenge faced by those applying the multiple chip module (MCM) technology to package multiple electronic chips into a single module. This challenge arises from the fact that a MCM module can function properly only if every chip assembled into this MCM package is individually a good die. Also, due to the accumulative effect, even a small percentage of reject rate for the individual chips generate an unacceptable loss to the MCM packages using these chips. For example, a 99% chip acceptance rate for the individual chips, when assembled into eight-chip modules (.times.8 modules) as dual in-line memory module (DIMM) or single-in-line-memory module (SIMM) packages, an 8% loss or rework rate is generated which is dearly unacceptable.
FIGS. 1A-1, 1A, 1B-1 and 1B are cross sectional views of a single chip-size-packaged (CSP) chip, and conventional multiple-chip-module assemblies implemented with multiple packaged chip-size package(CSP) and thin small outline package (TSOP) chips mounted on lead frames respectively. Referring to FIG. 1A-1, the intergrated circuit (IC) chip is mounted on a substrate and individually packaged as a CSP packaged chip. In FIG. 1A, three of these packaged CSP of FIGS. 1A-a are mounted on a multiple-chip-module (MCM) board. Each of these packaged CSP chip must be individually burned in and tested to assure each CSP chip is a know good die (KGD) before they are mounted on the MCM borad. Similarly, in FIG. 1B-1, a TSOP chip is mounted on a lead-frame and each of the TSOP chips must also be individually tested, burned in an tested again to assure every single TSOP chip is a KGD. Then a multiple of these individually tested TSOP chips mounted on lead frames are mounted on a MCM board for assembling into a MCM module. The conventional configuration and processes of assembling the MCM module require more production times, manufacturing processes, and higher costs due to the requirement of assuring only KGD chips are used to achieve a higher production yield.
In order to reduce wastes of resources committed to packaging chips which are not good dice, burn-in tests of individual chips are performed to identify the known good dice (DGD) before a MCM packaging processes are carried out. However, the processes for burning-in each individual chip or chip-size package (CSP) are very expensive due to the requirements of special testing sockets, and large dedicated burn-in board. Furthermore, difficult handling techniques are required to test these individual chips. Due to these special and expensive requirements for qualifying an intergrated circuit (IC) chip as known good die (KGD), it generally cost more to test a chip than to test a package. For the same reasons, the price of a known good die is much higher than the untested "burned in" packaged chips. Even with the high cost of testing and a much higher price to use the KGD, due to the concern of accumulative losses when chips are assembled as multiple chip modules, there is no choice but to employ the KGDs.
As shown in FIGS. 1A and 1B, the conventional multiple-chip-module (MCM) assemblies employ a two-level configuration. A two level configuration consists of either packaged chips with a first level substrate for packaging individual chip or a lead-frame for individual chip where known good chips are required on the MCM board. The individual chips supported on the lead-frame or the first level substrate are then mounted on a multiple chip module (MCM) board. The MCM board constitutes a second level substrate used for mounting multiple of individually packaged or lead-frame-supported chips. Additional cost are incurred in this two level substrate structure since it requires more material and processing. The device performance is also adversely affected due to slower signal transmission with additional capacitance resulted from structures of more levels. This two-level structure further presents another disadvantage that the packages have a high profile. In order to enhance device miniaturization, more and more modem applications implemented with packaged electronic chips require a reduced thickness and height. Conventional MCM packages implemented with a two-level substrate structure have very limited usefulness in modern miniaturized devices when the device requires multiple IC chips to be assembled and packaged with a very high density having small assembly size and thickness.
Therefore, a need still exists in the art to provide an improved configuration and procedure for testing and packaging the multiple chip modules. In addition to cost reduction by simplifying the test processes, the new configuration must also satisfy the need to more conveniently and economically reuse the known good dice when a known good die is packaged with other failed chips into a multiple-chip-module.